The parasitic BJT is a basic component in traditional bandgap reference and thermal sensor circuit designs. Various designs based on the parasitic BJT are described in Philip K. T. Mok and Ka Nang Leung, “Design Considerations of Recent Advanced Low-Voltage Low-Temperature-Coefficient CMOS Bandgap Voltage Reference”, IEEE 2004 Custom Integrated Circuits Conference, which is incorporated by reference herein. However, in advanced processes such as 20 nm and below FinFET processes, the P/N junction of the parasitic BJT has poor performance. These gate length nanometer devices have short gate lengths and thus high p+ source/drain doping to improve the device speed. However, they suffer from large leakage current. The PMOS p-type source/drain regions are changed from a p+ dopant like boron to a deposited SiGe epitaxial layer to improve current performance. This changes the P-type portion of the parasitic PNP BJT to SiGe. With this changes, however, a P/N junction of the parasitic BJT is changed from a homojunction to a heterojunction. Extra masking steps are required to remove the SiGe epitaxial layer of the parasitic SiGe BJT to provide better linearity performance of the I-V curve.